Applying HLS to FPGA Data Preprocessing in the Advanced Particle-astrophysics Telescope

• Main Author: Konst, Meagan
• Format: Text
• Language: English
• Published: Washington University Open Scholarship 2022
• Subjects: HLS; ADAPT; FPGA; Telescope; WashU; Optimization; Computer and Systems Architecture; Computer Engineering; Digital Circuits; Engineering; Hardware Systems; Antarctic; The Antarctic; Antarc*
• Online Access: https://openscholarship.wustl.edu/eng_etds/764; https://openscholarship.wustl.edu/cgi/viewcontent.cgi?article=1830&context=eng_etds

The Advanced Particle-astrophysics Telescope (APT) and its preliminary iteration the Antarctic Demonstrator for APT (ADAPT) are highly collaborative projects that seek to capture gamma-ray emissions. Along with dark matter and ultra-heavy cosmic ray nuclei measurements, APT will provide sub-degree localization and polarization measurements for gamma-ray transients. This will allow for devices on Earth to point to the direction from which the gamma-ray transients originated in order to collect additional data. The data collection process is as follows. A scintillation occurs and is detected by the wavelength-shifting fibers. This signal is then read by an ASIC and stored in an ADC buffer. This buffer is then formatted as a data packet with a meaningful header and stored in memory that is accessible by an FPGA. This is where the data must be preprocessed before being sent on to the CPU for the localization algorithms. This preprocessing includes capacitive memory pedestal subtraction and taking four trigger-relative time integrals per channel. There are 16 channels per ASIC. The HLS implementation of this FPGA data preprocessing seeks to answer the following questions. How well can HLS map this naïve C preprocessing model to an FPGA image? What HLS optimizations are most useful for this application? What are the reported latencies of these optimized models? How much chip area is consumed by each of these designs? How many ASICs can be processed by one FPGA?