Advanced equalization circuit techniques for high-speed 4-level pulse amplitude modulation (PAM-4) serial links

• Main Author: Wang, Can
• Format: Thesis
• Language: English
• Published: 2020
• Subjects: Pulse amplitude modulation; Signal processing; Equalizers (Electronics); Ethernet (Local area network system); Energy conservation; DML
• Online Access: http://repository.ust.hk/ir/Record/1783.1-109093; https://doi.org/10.14711/thesis-991012879860303412; http://repository.ust.hk/ir/bitstream/1783.1-109093/1/th_redirect.html

Global IP traffic is predicted to triple in five years since 2016. The coming 5G mobile network deployment aim at providing higher bandwidth to each user, together with internet of things, poses stringent demand on ethernet infrastructures. Big data and cloud computing driven by AI/machine learning, generates tremendous data traffic. All of them combine together, pushes the data rate beyond 100Gbps at every interface. Higher data rate comes with server channel loss at Nyquist frequency and more demanding on power in order to provide enough gain. The increasing power consumption not only adds extra operation cost but also reduce reliability. Especially in data centers, where the cooling system consumes a significant amount of power, urges us to reduce the power consumption so as to improve the energy efficiency and reliability. The current mainstream Ethernet standard is developing from 100 Gb/s to the next generation 200-400 Gb/s standard. Since the existing electrical/optical interconnect chips supporting 100 Gb/s cannot meet the speed requirements of the next generation Ethernet standard, industry and academia are researching and formulating solutions for the next generation Ethernet 200-400 Gb/s. Therefore, there is an urgent need to research and design electrical/optical interconnect chips to support the 200-400 Gb/s standard. Non-return-to-zero (NRZ) signaling has been the mainstream modulation scheme for data rate below 40Gb/s due to its simplicity. As the data rate goes beyond 50Gb/s NRZ signaling faces server channel loss. The 4-level pulse amplitude modulation becomes popular when data rate > 50Gbps since it transmits 2 bits a time to lower the signal Nyquist frequency. PAM-4 signaling with doubled bandwidth efficiency is a promising solution for energy efficient 200-400 Gb/s transceiver design. In this thesis, an energy efficient continuous time linear equalizer (CTLE) works at 52Gb/s and a 56Gb/s DML laser driver front-end using piece-wise feed-forward equalizer that compensates for laser nonlinearities are presented. The first work presents a low-power PAM-4 receiver for very-short reach (VSR) applications enabled by the proposed single-stage multiple peaking CTLE, fabricated in 40-nm TSMC CMOS process. A wide bandwidth phase lock loop (WBW-PLL) is utilized to avoid the free running frequency shift and suppress the intrinsic phase noise of the ring oscillator, provides a low-jitter clocking performance with low power consumption. With a voltage-controlled delay line (VCDL) adjusted by a bang-bang phase detector and a charge pump, the data phase is recovered. This receiver IC achieves a bit efficiency of 0.92 pJ/bit/s while compensating for 7.3-dB channel loss at 13 GHz. The second work presents a novel transmitter-side piece-wise feed-forward equalization circuit that compensates for laser/modulator nonlinearities. PAM-4 is very sensitive to inter-symbol interference caused by laser diode nonidealities such as limited bandwidth, dynamic bandwidth variations with respect to signal levels. This method implements 3 unary data signals to synthesize one PAM-4 signal by a summer at the final output stage. Feedforward equalization coefficients are generated according to each unary data pattern and the peaking frequency for each unary data can be adjusted independently. With linear superposition assumption, it can generate all the equalization coefficients for different transitions. The piece-wise equalization is simulated with compact Verilog-A DFB laser nonlinear model using the simulation in 40-nm TSMC CMOS process.