| Summary: | Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. Engineering and Applied Science Bibliography: leaves 100-102 This thesis shows how to compile a program expressed by a novel hardware description language, the State Machine Algol-Like Language (SMALL), into Field- Programmable Gate Arrays (FPGAs). A "netlist generator" for the SMALL language is created to transform a parallel Algorithmic State Machine (ASM) chart into a structural VHDL description. The one-hot encoding technique is used for the transformations. The structural VHDL description for the netlist is simulated and synthesised by Synopsys VSS (VHDL System Simulator) and Synopsys FPGA Compiler, respectively. The netlist is very simple and the components of the netlist consist of only D-type flip-flops and basic gates. The Design Manager of the Xilinx Alliance Series version 1.4 is used to produce configuration data for Xilinx FPGA chips. The Xilinx XC4000 family is employed as the target FPGA device. -- The simulation results for several SMALL programs indicate that the netlist generator performs the specified requirements for all the statements and all the operators in the SMALL language. -- Using the netlist generator and existing place-and-route tools makes the implementation of SMALL programs on FPGAs easy. This research offers a significant advance on the original SMALL implementation. Due to its simplicity and simple semantics, it is believed that the SMALL language will be widely used in many areas in the future.
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