Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems
The Jicamarca Radio Observatory (JRO) is part of the Western Hemisphere chain of Incoherent Scatter Radar (ISR) observatories which extends from Lima, Peru to S0ndre Str0mfjord, Greenland. The equatorial ionosphere is studied only by JRO in the world. The Observatory is a facility of the Instituto G...
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ftinstgpperu:oai:repositorio.igp.gob.pe:20.500.12816/3065 2023-07-30T04:03:54+02:00 Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems Rojas, John Verástegui, Joaquín Milla, Marco 2018-01 application/pdf https://hdl.handle.net/20.500.12816/3065 https://doi.org/10.1109/ECON.2017.8247311 eng eng Institute of Electrical and Electronics Engineers urn:isbn:9781538622780 Rojas, J., Verástegui, J., & Milla, M. (2018). Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems.==$2017 Electronic Congress (E-CON UNI),$==22-24 Nov. 2017, Lima, Peru. https://doi.org/10.1109/ECON.2017.8247311 index-oti2018 http://hdl.handle.net/20.500.12816/3065 https://doi.org/10.1109/ECON.2017.8247311 info:eu-repo/semantics/restrictedAccess FPGA LVDS Double buffering Gigabit Ethernet UDP Threads of execution http://purl.org/pe-repo/ocde/ford#1.05.01 info:eu-repo/semantics/conferenceObject 2018 ftinstgpperu https://doi.org/20.500.12816/306510.1109/ECON.2017.8247311 2023-07-17T16:50:54Z The Jicamarca Radio Observatory (JRO) is part of the Western Hemisphere chain of Incoherent Scatter Radar (ISR) observatories which extends from Lima, Peru to S0ndre Str0mfjord, Greenland. The equatorial ionosphere is studied only by JRO in the world. The Observatory is a facility of the Instituto Geofísico del PerU operated with support from the US National Science Foundation Cooperative Agreements through Cornell University. One of the main radar components is JARS (Jicamarca Acquisition Radar System), which functionality is based on CPLDs (Complex Programmable Logic Device) to configure the system and transfer the data from the digital receivers to the acquisition computer over a proprietary interface NI PCIe-6537. However due to some limitations as its high cost, driver updates dependency and the data transfer speed, it was necessary to replace this interface with the design and implementation of a high-speed hardware, embedded on FPGA devices, to transmit the data through the LVDS interface to a double buffering stage, and forward these as packets on the standard Gigabit Ethernet, based on the IEEE 802.3 protocol and using the UDP protocol. In this way, this development will allow to update the hardware of the current JARS to get a low cost portable system and to work with the required bandwidth. A prototype of this system was developed on the JRO and also a customized software was written, based on UDP socket and multiple threads of execution. Conference Object Greenland Repositorio Geofísico Naciona del Perú Greenland 2017 Electronic Congress (E-CON UNI) 1 4 |
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FPGA LVDS Double buffering Gigabit Ethernet UDP Threads of execution http://purl.org/pe-repo/ocde/ford#1.05.01 |
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FPGA LVDS Double buffering Gigabit Ethernet UDP Threads of execution http://purl.org/pe-repo/ocde/ford#1.05.01 Rojas, John Verástegui, Joaquín Milla, Marco Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
topic_facet |
FPGA LVDS Double buffering Gigabit Ethernet UDP Threads of execution http://purl.org/pe-repo/ocde/ford#1.05.01 |
description |
The Jicamarca Radio Observatory (JRO) is part of the Western Hemisphere chain of Incoherent Scatter Radar (ISR) observatories which extends from Lima, Peru to S0ndre Str0mfjord, Greenland. The equatorial ionosphere is studied only by JRO in the world. The Observatory is a facility of the Instituto Geofísico del PerU operated with support from the US National Science Foundation Cooperative Agreements through Cornell University. One of the main radar components is JARS (Jicamarca Acquisition Radar System), which functionality is based on CPLDs (Complex Programmable Logic Device) to configure the system and transfer the data from the digital receivers to the acquisition computer over a proprietary interface NI PCIe-6537. However due to some limitations as its high cost, driver updates dependency and the data transfer speed, it was necessary to replace this interface with the design and implementation of a high-speed hardware, embedded on FPGA devices, to transmit the data through the LVDS interface to a double buffering stage, and forward these as packets on the standard Gigabit Ethernet, based on the IEEE 802.3 protocol and using the UDP protocol. In this way, this development will allow to update the hardware of the current JARS to get a low cost portable system and to work with the required bandwidth. A prototype of this system was developed on the JRO and also a customized software was written, based on UDP socket and multiple threads of execution. |
format |
Conference Object |
author |
Rojas, John Verástegui, Joaquín Milla, Marco |
author_facet |
Rojas, John Verástegui, Joaquín Milla, Marco |
author_sort |
Rojas, John |
title |
Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
title_short |
Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
title_full |
Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
title_fullStr |
Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
title_full_unstemmed |
Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems |
title_sort |
design and implementation of a high speed interface system over gigabit ethernet based on fpga for use on radar acquisition systems |
publisher |
Institute of Electrical and Electronics Engineers |
publishDate |
2018 |
url |
https://hdl.handle.net/20.500.12816/3065 https://doi.org/10.1109/ECON.2017.8247311 |
geographic |
Greenland |
geographic_facet |
Greenland |
genre |
Greenland |
genre_facet |
Greenland |
op_relation |
urn:isbn:9781538622780 Rojas, J., Verástegui, J., & Milla, M. (2018). Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems.==$2017 Electronic Congress (E-CON UNI),$==22-24 Nov. 2017, Lima, Peru. https://doi.org/10.1109/ECON.2017.8247311 index-oti2018 http://hdl.handle.net/20.500.12816/3065 https://doi.org/10.1109/ECON.2017.8247311 |
op_rights |
info:eu-repo/semantics/restrictedAccess |
op_doi |
https://doi.org/20.500.12816/306510.1109/ECON.2017.8247311 |
container_title |
2017 Electronic Congress (E-CON UNI) |
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