Implementation of advanced ball printing technology for high yield bumping of wafer chip scale packages
S.298-303 Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder paste print & reflow techniques can be utilized but the resultant bumps invariably fall below specifications due to process limitations. More commonly, dedicated equipment is...
| Published in: | 2005 7th Electronic Packaging Technology Conference |
|---|---|
| Main Authors: | , , , , , |
| Format: | Conference Object |
| Language: | English |
| Published: |
2005
|
| Subjects: | |
| Online Access: | https://publica.fraunhofer.de/handle/publica/348369 https://doi.org/10.1109/EPTC.2005.1614410 |
| Summary: | S.298-303 Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder paste print & reflow techniques can be utilized but the resultant bumps invariably fall below specifications due to process limitations. More commonly, dedicated equipment is used for the placement of pre-formed solder spheres on the wafer pads. This paper details work undertaken to combine the benefits of standard stencil printer technology with that of solid solder sphere placement to enable the development of a low cost, flexible system for the bumping of wafer level packages. Actual preform-ball printing takes place by using the same standard stencil printer equipment as for solder paste printing. Prior to ball print, flux is printed on the wafer pads by screen printing. The work undertaken forms part of the European funded "Blue Whale" program which is concerned with developing next generation wafer level packaging for handheld applications in a LAN environment. The present paper details all the technology developments taking place throughout the project to achieve balling at 500µm and 400µm pitch area array configurations with 300µm and 250µm balls, respectively. The work performed greatly contributes to the advancement of balling capabilities using standard printing technology by further lowering the bump pitch of conventional WLCSP's. Tests were performed with both the Power transistor 6-wafer design (placing 300?m spheres on a 500µm pitch) and the RT07 System on Chip 8 wafer design (250µm spheres on a 400µm pitch). Both eutectic Sn63Pb37 and Pb-free spheres were printed on the wafers. |
|---|