| Summary: | S.143-148 In order to reduce possible reliability risks in the early stage of package design, the development of new package types requires a pre-understanding of their thermal and thermo-mechanical behavior. The current paper concentrates on a virtual design approach for new types of wafer level packages which have been the focus of the EU-project Blue Whale. The packages involve Power transistor and RF System-on-Chip design concepts. The simulations are used to estimate intrinsic stresses which occur as a result of the manufacturing processes. Furthermore, the reliability behavior at second level assembly is being addressed and is mainly concerned with the reliability of the solder interconnects and the thermal behavior of the packages. For the power transistor, an interesting feature is the micro-via on the silicon chip. Stresses and strains inside and around this via are critical to the reliability of the package. Therefore, they have become the subject of a parametric analysis which leads to important design guidelines.
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