A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-B Booth Multiplier in 16-nm FinFET

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16 × 16 -b Booth multipl...

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Bibliographic Details
Main Authors: ESSCIRC ESSDERC 2021 2021, Fish, Alexander, Lanuzza, Marco, Shavit, Netanel, Stanger, Inbal, Taco, Ramiro
Format: Article in Journal/Newspaper
Language:unknown
Published: Underline Science Inc. 2021
Subjects:
Design Engineering
Electronics and Instrumentation
Electronic Circuits
DML
Online Access:https://dx.doi.org/10.48448/5bxt-qf75
https://underline.io/lecture/32731-a-08-v-154-pjdash940-mhz-dual-mode-logic-based-1616-b-booth-multiplier-in-16-nm-finfet
Description
Summary:The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16 × 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

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