REFERENCES
The DML static mode demonstrated the lowest energy dissipation: 2.2 × less than CMOS on average, and 5 × less than the domino. We presented a basic proof-of-concept of the proposed DML logic by measurements of an 80-nm test chip. Future work will include the optimization of the DML gates for operati...
| Main Authors: | , , , , , |
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| Format: | Text |
| Language: | English |
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| Online Access: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.640.4534 http://www.ece.rochester.edu/users/friedman/papers/TVLSI_13_Link_breaking.pdf |
| Summary: | The DML static mode demonstrated the lowest energy dissipation: 2.2 × less than CMOS on average, and 5 × less than the domino. We presented a basic proof-of-concept of the proposed DML logic by measurements of an 80-nm test chip. Future work will include the optimization of the DML gates for operation with standard supply voltages, development of a standard library and designing of a benchmark design using a standard ASIC flow. |
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