Hardware Support for Fast Capability-based Addressing

Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to recordaccess permissions for processes. With the advent of computers that support cycle-by-cycle multithreading, protection schemes that increase the time to p...

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Bibliographic Details
Main Authors: Nicholas Carter, Stephen W. Keckler, William J. Dally
Other Authors: The Pennsylvania State University CiteSeerX Archives
Format: Text
Language:English
Published: 1994
Subjects:
Online Access:http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.38.6552
Description
Summary:Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to recordaccess permissions for processes. With the advent of computers that support cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments. This paper examines guarded pointers, a hardware technique which uses tagged 64-bit pointer objects to implement capabilitybased addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one l.