Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder
International audience This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a...
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Online Access: | https://hal.archives-ouvertes.fr/hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329/document https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf https://doi.org/10.3390/electronics10091052 |
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ftccsdartic:oai:HAL:hal-03218329v1 2023-05-15T16:02:01+02:00 Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder Vicuña, Kevin Mosquera, Cristhopher Musello, Ariana Benedictis, Sara Rendón, Mateo Garzón, Esteban Prócel, Luis, Trojman, Lionel Taco, Ramiro Universidad San Francisco de Quito (USFQ) Università della Calabria Arcavacata di Rende (Unical) Laboratoire d'Informatique, Signal et Image, Electronique et Télécommunication (LISITE) Institut Supérieur d'Electronique de Paris (ISEP) 2021 https://hal.archives-ouvertes.fr/hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329/document https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf https://doi.org/10.3390/electronics10091052 en eng HAL CCSD Penton Publishing Inc. info:eu-repo/semantics/altIdentifier/doi/10.3390/electronics10091052 hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329/document https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf doi:10.3390/electronics10091052 info:eu-repo/semantics/OpenAccess ISSN: 0883-4989 Electronics https://hal.archives-ouvertes.fr/hal-03218329 Electronics, Penton Publishing Inc., 2021, 10 (9), pp.1052. ⟨10.3390/electronics10091052⟩ self-adaptive Dual Mode Logic controller address decoder [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics info:eu-repo/semantics/article Journal articles 2021 ftccsdartic https://doi.org/10.3390/electronics10091052 2021-05-08T22:21:35Z International audience This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. Article in Journal/Newspaper DML Archive ouverte HAL (Hyper Article en Ligne, CCSD - Centre pour la Communication Scientifique Directe) Electronics 10 9 1052 |
institution |
Open Polar |
collection |
Archive ouverte HAL (Hyper Article en Ligne, CCSD - Centre pour la Communication Scientifique Directe) |
op_collection_id |
ftccsdartic |
language |
English |
topic |
self-adaptive Dual Mode Logic controller address decoder [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics |
spellingShingle |
self-adaptive Dual Mode Logic controller address decoder [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Vicuña, Kevin Mosquera, Cristhopher Musello, Ariana Benedictis, Sara Rendón, Mateo Garzón, Esteban Prócel, Luis, Trojman, Lionel Taco, Ramiro Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
topic_facet |
self-adaptive Dual Mode Logic controller address decoder [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics |
description |
International audience This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. |
author2 |
Universidad San Francisco de Quito (USFQ) Università della Calabria Arcavacata di Rende (Unical) Laboratoire d'Informatique, Signal et Image, Electronique et Télécommunication (LISITE) Institut Supérieur d'Electronique de Paris (ISEP) |
format |
Article in Journal/Newspaper |
author |
Vicuña, Kevin Mosquera, Cristhopher Musello, Ariana Benedictis, Sara Rendón, Mateo Garzón, Esteban Prócel, Luis, Trojman, Lionel Taco, Ramiro |
author_facet |
Vicuña, Kevin Mosquera, Cristhopher Musello, Ariana Benedictis, Sara Rendón, Mateo Garzón, Esteban Prócel, Luis, Trojman, Lionel Taco, Ramiro |
author_sort |
Vicuña, Kevin |
title |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_short |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_fullStr |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full_unstemmed |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_sort |
energy efficient self-adaptive dual mode logic address decoder |
publisher |
HAL CCSD |
publishDate |
2021 |
url |
https://hal.archives-ouvertes.fr/hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329/document https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf https://doi.org/10.3390/electronics10091052 |
genre |
DML |
genre_facet |
DML |
op_source |
ISSN: 0883-4989 Electronics https://hal.archives-ouvertes.fr/hal-03218329 Electronics, Penton Publishing Inc., 2021, 10 (9), pp.1052. ⟨10.3390/electronics10091052⟩ |
op_relation |
info:eu-repo/semantics/altIdentifier/doi/10.3390/electronics10091052 hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329 https://hal.archives-ouvertes.fr/hal-03218329/document https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf doi:10.3390/electronics10091052 |
op_rights |
info:eu-repo/semantics/OpenAccess |
op_doi |
https://doi.org/10.3390/electronics10091052 |
container_title |
Electronics |
container_volume |
10 |
container_issue |
9 |
container_start_page |
1052 |
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1766397662781767680 |