Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

International audience This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a...

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Bibliographic Details
Published in:Electronics
Main Authors: Vicuña, Kevin, Mosquera, Cristhopher, Musello, Ariana, Benedictis, Sara, Rendón, Mateo, Garzón, Esteban, Prócel, Luis, Trojman, Lionel, Taco, Ramiro
Other Authors: Universidad San Francisco de Quito (USFQ), Università della Calabria Arcavacata di Rende (Unical), Laboratoire d'Informatique, Signal et Image, Electronique et Télécommunication (LISITE), Institut Supérieur d'Electronique de Paris (ISEP)
Format: Article in Journal/Newspaper
Language:English
Published: HAL CCSD 2021
Subjects:
self-adaptive
Dual Mode Logic
controller
address decoder
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
DML
Online Access:https://hal.archives-ouvertes.fr/hal-03218329
https://hal.archives-ouvertes.fr/hal-03218329/document
https://hal.archives-ouvertes.fr/hal-03218329/file/DML.pdf
https://doi.org/10.3390/electronics10091052
Description
Summary:International audience This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

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