Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

• Published in: Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit
• Main Authors: Britton, B.K., Oh, Y.T., Oswald, W., Nguyen, H.T., Singh, S., Lee, G., Wai-Bor Leung, Spivak, C., Steward, J., Chen, C.T.
• Format: Conference Object
• Language: unknown
• Published: IEEE 2002
• Subjects: Orca
• Online Access: http://dx.doi.org/10.1109/asic.1994.404516; http://xplorestaging.ieee.org/ielx2/3197/9098/00404516.pdf?arnumber=404516