Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs
Published in: | Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit |
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Main Authors: | , , , , , , , , , |
Format: | Conference Object |
Language: | unknown |
Published: |
IEEE
2002
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Subjects: | |
Online Access: | http://dx.doi.org/10.1109/asic.1994.404516 http://xplorestaging.ieee.org/ielx2/3197/9098/00404516.pdf?arnumber=404516 |
Description not available. |