Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA
In this paper we present an ad-hoc architecture for on-board Deep Learning (DL) network implemented onto rad-tol FPGA, creating building blocks re-usable for different AI solutions or networks to be developed in the future. The problem analysed is based on autonomous descent and landing scenario, tr...
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ftzenodo:oai:zenodo.org:5520545 2024-09-15T18:24:59+00:00 Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA D. Gogu F. Stancu A. Pastor González D. Fortún Sánchez D. Gonzalez-Arjona O. Müler M. Barbelian V. Pana 2021-06-14 https://doi.org/10.5281/zenodo.5520545 eng eng Zenodo https://zenodo.org/communities/obdp2021 https://doi.org/10.5281/zenodo.5520544 https://doi.org/10.5281/zenodo.5520545 oai:zenodo.org:5520545 info:eu-repo/semantics/openAccess Creative Commons Attribution 4.0 International https://creativecommons.org/licenses/by/4.0/legalcode OBDP2021, OBDP2021 - 2nd European Workshop on On-Board Data Processing, 14-17 June 2021 obdp obdp2021 on-board processing info:eu-repo/semantics/conferencePaper 2021 ftzenodo https://doi.org/10.5281/zenodo.552054510.5281/zenodo.5520544 2024-07-25T11:21:12Z In this paper we present an ad-hoc architecture for on-board Deep Learning (DL) network implemented onto rad-tol FPGA, creating building blocks re-usable for different AI solutions or networks to be developed in the future. The problem analysed is based on autonomous descent and landing scenario, trying to compare traditional techniques. The implementation of the Deep Learning algorithm is focused on extraction of features in navigation camera images. The solution in FPGA allows a reduced power consumption while maximizing the execution performance, opposite to some, or many, on-ground solutions. A space representative breadboard is prepared to demonstrate the solution. For training/testing/validating of the Deep Learning (DL) it has been selected the North Pole of the Moon surface, where one trajectory is used to train the DL and a second one to validate the DL. The architecture of the neural network is divided in numerous layers and it is based on Processing Units (PU), where on layer can have multiple PU. Each PU has the possibility to perform operations such as Convolution, MaxPooling and Upsampling. The implementation is compose by a set of PUs, three DSPs and a controller. The controller is responsible of the coordination of reading and writing commands into the external memory, as well as deciding which operation to execute. Whereas lower address of the memory is allocated for storage the parameters necessary for the operations (weights and biases), once the FPGA is initialized, the following memory addresses is reserved for the input images. Moreover, each layer has a fraction of the RAM reserved for its. Autonomous Navigation Based is a complex DL implementation and presents a lot of challenges, but two of them are of outmost importance: FPGA resources and timing performances. Both terms are completely correlated and the design is tailored in order to balance the bottleneck, the output performance based on timing requirements and the number of accesses to external memory. This architecture requires of a ... Conference Object North Pole Zenodo |
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obdp obdp2021 on-board processing |
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obdp obdp2021 on-board processing D. Gogu F. Stancu A. Pastor González D. Fortún Sánchez D. Gonzalez-Arjona O. Müler M. Barbelian V. Pana Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
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obdp obdp2021 on-board processing |
description |
In this paper we present an ad-hoc architecture for on-board Deep Learning (DL) network implemented onto rad-tol FPGA, creating building blocks re-usable for different AI solutions or networks to be developed in the future. The problem analysed is based on autonomous descent and landing scenario, trying to compare traditional techniques. The implementation of the Deep Learning algorithm is focused on extraction of features in navigation camera images. The solution in FPGA allows a reduced power consumption while maximizing the execution performance, opposite to some, or many, on-ground solutions. A space representative breadboard is prepared to demonstrate the solution. For training/testing/validating of the Deep Learning (DL) it has been selected the North Pole of the Moon surface, where one trajectory is used to train the DL and a second one to validate the DL. The architecture of the neural network is divided in numerous layers and it is based on Processing Units (PU), where on layer can have multiple PU. Each PU has the possibility to perform operations such as Convolution, MaxPooling and Upsampling. The implementation is compose by a set of PUs, three DSPs and a controller. The controller is responsible of the coordination of reading and writing commands into the external memory, as well as deciding which operation to execute. Whereas lower address of the memory is allocated for storage the parameters necessary for the operations (weights and biases), once the FPGA is initialized, the following memory addresses is reserved for the input images. Moreover, each layer has a fraction of the RAM reserved for its. Autonomous Navigation Based is a complex DL implementation and presents a lot of challenges, but two of them are of outmost importance: FPGA resources and timing performances. Both terms are completely correlated and the design is tailored in order to balance the bottleneck, the output performance based on timing requirements and the number of accesses to external memory. This architecture requires of a ... |
format |
Conference Object |
author |
D. Gogu F. Stancu A. Pastor González D. Fortún Sánchez D. Gonzalez-Arjona O. Müler M. Barbelian V. Pana |
author_facet |
D. Gogu F. Stancu A. Pastor González D. Fortún Sánchez D. Gonzalez-Arjona O. Müler M. Barbelian V. Pana |
author_sort |
D. Gogu |
title |
Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
title_short |
Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
title_full |
Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
title_fullStr |
Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
title_full_unstemmed |
Boosting Autonomous Navigation solution based on Deep Learning using new rad-tol Kintex Ultrascale FPGA |
title_sort |
boosting autonomous navigation solution based on deep learning using new rad-tol kintex ultrascale fpga |
publisher |
Zenodo |
publishDate |
2021 |
url |
https://doi.org/10.5281/zenodo.5520545 |
genre |
North Pole |
genre_facet |
North Pole |
op_source |
OBDP2021, OBDP2021 - 2nd European Workshop on On-Board Data Processing, 14-17 June 2021 |
op_relation |
https://zenodo.org/communities/obdp2021 https://doi.org/10.5281/zenodo.5520544 https://doi.org/10.5281/zenodo.5520545 oai:zenodo.org:5520545 |
op_rights |
info:eu-repo/semantics/openAccess Creative Commons Attribution 4.0 International https://creativecommons.org/licenses/by/4.0/legalcode |
op_doi |
https://doi.org/10.5281/zenodo.552054510.5281/zenodo.5520544 |
_version_ |
1810465375814418432 |