Extending magny-cours cache coherence
One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like HyperTransport. Unfortunately, HyperTransport addressing limitations prevent build...
Published in: | IEEE Transactions on Computers |
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Main Authors: | , , , , , , , |
Other Authors: | , , , |
Format: | Article in Journal/Newspaper |
Language: | English |
Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2012
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Subjects: | |
Online Access: | http://hdl.handle.net/10251/36257 https://doi.org/10.1109/TC.2011.65 |