Multi-Target Vectorization with MTPS C++ Generic Library

• Main Authors: Kirschenmann, Wilfried, Plagne, Laurent, Vialle, Stéphane
• Other Authors: EDF (EDF), Algorithms for the Grid (ALGORILLE), INRIA Lorraine, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Institut National de Recherche en Informatique et en Automatique (Inria)-Université Henri Poincaré - Nancy 1 (UHP)-Université Nancy 2-Institut National Polytechnique de Lorraine (INPL)-Centre National de la Recherche Scientifique (CNRS)-Université Henri Poincaré - Nancy 1 (UHP)-Université Nancy 2-Institut National Polytechnique de Lorraine (INPL)-Centre National de la Recherche Scientifique (CNRS), IMS : Information, Multimodalité & Signal, SUPELEC-Campus Metz, Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE), Kristján Jónasson
• Format: Conference Object
• Language: English
• Published: HAL CCSD 2010
• Subjects: [INFO.INFO-DC]Computer Science [cs]/Distributed; Parallel; and Cluster Computing [cs.DC]; Reykjavík; Iceland
• Online Access: https://centralesupelec.hal.science/hal-00685159; https://centralesupelec.hal.science/hal-00685159/document; https://centralesupelec.hal.science/hal-00685159/file/WK_Para2010_LNCS7134.pdf; https://doi.org/10.1007/978-3-642-28145-7_33

International audience This article introduces a C++ template library dedicated at vectorizing algorithms for different target architectures: Multi-Target Parallel Skeleton (MTPS). Skeletons describing the data structures and algorithms are provided and allow MTPS to generate a code with optimized memory access patterns for the choosen architecture. MTPS currently supports x86-64 multicore CPUs and CUDA enabled GPUs. On these architectures, performances close to hardware limits are observed.