Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize t...

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Published in:ACM Transactions on Reconfigurable Technology and Systems
Main Authors: Hogervorst, T.A. (author), Nane, R. (author), Marchiori, Giacomo (author), Qiu, Tong Dong (author), Blatt, Markus (author), Rustad, Alf Birger (author)
Format: Article in Journal/Newspaper
Language:English
Published: 2022
Subjects:
CFD
GPU
HPC
Online Access:http://resolver.tudelft.nl/uuid:695b9a87-d7b5-4076-aac4-1418c394da67
https://doi.org/10.1145/3476229
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spelling fttudelft:oai:tudelft.nl:uuid:695b9a87-d7b5-4076-aac4-1418c394da67 2024-02-11T10:06:00+01:00 Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays Hogervorst, T.A. (author) Nane, R. (author) Marchiori, Giacomo (author) Qiu, Tong Dong (author) Blatt, Markus (author) Rustad, Alf Birger (author) 2022 http://resolver.tudelft.nl/uuid:695b9a87-d7b5-4076-aac4-1418c394da67 https://doi.org/10.1145/3476229 en eng http://www.scopus.com/inward/record.url?scp=85125839675&partnerID=8YFLogxK ACM Transactions on Reconfigurable Technology and Systems--1936-7406--bad18339-a5aa-41ea-b134-be1ae50cd080 http://resolver.tudelft.nl/uuid:695b9a87-d7b5-4076-aac4-1418c394da67 https://doi.org/10.1145/3476229 © 2022 T.A. Hogervorst, R. Nane, Giacomo Marchiori, Tong Dong Qiu, Markus Blatt, Alf Birger Rustad BiCGStab CFD FPGA GPU HPC ILU0 Iterative solvers journal article 2022 fttudelft https://doi.org/10.1145/3476229 2024-01-24T23:34:49Z Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. Field-Programmable Gate Arrays could accelerate scientific computing because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers. In this article, we study the potential of using Field-Programmable Gate Arrays in High-Performance Computing because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we propose a novel Sparse Matrix-Vector multiplication unit and an ILU0 preconditioner tightly integrated with a BiCGStab solver kernel. We integrate the developed preconditioned iterative solver in Flow from the Open Porous Media project, a state-of-the-art open source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both stand-alone mode and integrated in the reservoir simulator, using the NORNE field, a real-world case reservoir model using a grid with more than 105 cells and using three unknowns per cell. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. Computer Engineering QCD/DiCarlo Lab Article in Journal/Newspaper Norne field Delft University of Technology: Institutional Repository ACM Transactions on Reconfigurable Technology and Systems 15 2 1 35
institution Open Polar
collection Delft University of Technology: Institutional Repository
op_collection_id fttudelft
language English
topic BiCGStab
CFD
FPGA
GPU
HPC
ILU0
Iterative solvers
spellingShingle BiCGStab
CFD
FPGA
GPU
HPC
ILU0
Iterative solvers
Hogervorst, T.A. (author)
Nane, R. (author)
Marchiori, Giacomo (author)
Qiu, Tong Dong (author)
Blatt, Markus (author)
Rustad, Alf Birger (author)
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
topic_facet BiCGStab
CFD
FPGA
GPU
HPC
ILU0
Iterative solvers
description Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. Field-Programmable Gate Arrays could accelerate scientific computing because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers. In this article, we study the potential of using Field-Programmable Gate Arrays in High-Performance Computing because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we propose a novel Sparse Matrix-Vector multiplication unit and an ILU0 preconditioner tightly integrated with a BiCGStab solver kernel. We integrate the developed preconditioned iterative solver in Flow from the Open Porous Media project, a state-of-the-art open source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both stand-alone mode and integrated in the reservoir simulator, using the NORNE field, a real-world case reservoir model using a grid with more than 105 cells and using three unknowns per cell. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. Computer Engineering QCD/DiCarlo Lab
format Article in Journal/Newspaper
author Hogervorst, T.A. (author)
Nane, R. (author)
Marchiori, Giacomo (author)
Qiu, Tong Dong (author)
Blatt, Markus (author)
Rustad, Alf Birger (author)
author_facet Hogervorst, T.A. (author)
Nane, R. (author)
Marchiori, Giacomo (author)
Qiu, Tong Dong (author)
Blatt, Markus (author)
Rustad, Alf Birger (author)
author_sort Hogervorst, T.A. (author)
title Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
title_short Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
title_full Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
title_fullStr Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
title_full_unstemmed Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
title_sort hardware acceleration of high-performance computational flow dynamics using high-bandwidth memory-enabled field-programmable gate arrays
publishDate 2022
url http://resolver.tudelft.nl/uuid:695b9a87-d7b5-4076-aac4-1418c394da67
https://doi.org/10.1145/3476229
genre Norne field
genre_facet Norne field
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op_rights © 2022 T.A. Hogervorst, R. Nane, Giacomo Marchiori, Tong Dong Qiu, Markus Blatt, Alf Birger Rustad
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