Domain Magnet Logic (DML): A new approach to magnetic circuits

• Published in: 14th IEEE International Conference on Nanotechnology
• Main Authors: CAIRO, FABRIZIO, VACCA, MARCO, GRAZIANO, MARIAGRAZIA, ZAMBONI, Maurizio
• Other Authors: Cairo, Fabrizio, Vacca, Marco, Graziano, Mariagrazia, Zamboni, Maurizio
• Format: Conference Object
• Language: English
• Published: IEEE - INST ELECTRICAL ELECTRONICS ENGINEERS INC 2014
• Subjects: CMOS logic circuit; adder; magnetic logic; magnetoelectronic; nanomagnetic; DML; NML circuit; Pentium-4 tree-adder; baptized domain magnet logic; circuit latency; interconnection wire; low power consumption; magnetic circuit; physical level simulation; post CMOS scenario nanomagnet logic; power dissipation; word length 32 bit; Clock; Integrated circuit interconnection; Magnetic domain wall; Magnetic domain; Magnetostatics
• Online Access: http://hdl.handle.net/11583/2588523; https://doi.org/10.1109/NANO.2014.6968053

In the post CMOS scenario NanoMagnets Logic (NML) has attracted a considerable attention due to its characteristic features. The ability to combine logic and memory in the same device, and a possible low power consumption, allows NML to overcome some of the CMOS intrinsic limitations. However, considering realistic circuit implementations where both theoretical and technological constraints are kept into account, performance could not be reduced with respect to the expectations. The reason lies in the fact that a huge area is wasted with interconnection wires. In this paper we propose a new approach to the conception of magnetic circuits, that we have baptized Domain Magnet Logic (DML). We embed domain walls in NML circuits in a technologically compatible solution, with the aim of improving interconnection performance. We have validated our solution with physical level simulations, and we show the improvements designing as a case study a complex and realistic circuit, a 32 bit Pentium-4 tree-adder. DML logic allows to reduce the circuit area up to 50%, with consequent dramatic improvements on circuit latency and power dissipation. This is a very good result itself, that represents just the tip of the iceberg of the amazing possibilities opened by this innovative approach.