WHOLE: A Low Energy I-Cache with Separate Way History
Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation. Previous energy-efficient approaches usually suffer from performance degradation and redundant extension bits. In this paper, we propose a Way History Oriented Low Energy Instruction Cache (WH...
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ftpekinguniv:oai:localhost:20.500.11897/260967 2023-05-15T18:32:44+02:00 WHOLE: A Low Energy I-Cache with Separate Way History Xie, Zichao Tong, Dong Cheng, Xu Xie, ZC (reprint author), Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China. Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China. 2009 https://hdl.handle.net/20.500.11897/260967 https://doi.org/10.1109/ICCD.2009.5413162 en eng 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN. 1057871 1063-6404 http://hdl.handle.net/20.500.11897/260967 doi:10.1109/ICCD.2009.5413162 WOS:000277251900022 EI SCI Conference 2009 ftpekinguniv https://doi.org/20.500.11897/260967 https://doi.org/10.1109/ICCD.2009.5413162 2021-08-01T09:01:26Z Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation. Previous energy-efficient approaches usually suffer from performance degradation and redundant extension bits. In this paper, we propose a Way History Oriented Low Energy Instruction Cache (WHOLE-Cache) design for single issue and in-order execution processors. The WHOLE-Cache design not only achieves a significant portion of energy reduction by effectively reducing dynamic energy dissipation of set-associative instruction cache, but also leads to no additional cycle penalties. Tag comparison results are stored into either the Branch Target Buffer (BTB) or the Instruction Cache (I-Cache) to avoid tag checks and unnecessary way activation for subsequent accesses to visited cache lines. The extended BTB uses way history bits for branch instructions, while the I-Cache extension bits are used in case of fetching consecutive instructions resided in different cache lines. A valid flag is associated with each stored tag comparison result to indicate whether the instruction to be fetched is resided in the recorded location. A simple invalidation scheme is implemented in the cache miss replacement operation. Whenever a cache line is replaced, the pointers to it, which reside in the BTB or other I-cache lines, will be invalidated accordingly. We model the WHOLE-Cache design in Verilog. By deriving basic parameters from TSMC 65nm technology, we use Wattch simulator to evaluate the performance and energy reduction of the WHOLE-Cache in the instruction fetch stage. We use SPEC2000 and Mediabench as benchmarks. It is observed that compared with a conventional 4-way set-associative I-Cache, the energy consumption of the WHOLE-Cache is reduced by 65% without any performance penalty. Computer Science, Hardware & Architecture Computer Science, Theory & Methods Engineering, Electrical & Electronic EI CPCI-S(ISTP) 1 Conference Object The Pointers Peking University Institutional Repository (PKU IR) 2009 IEEE International Conference on Computer Design 137 143 |
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Peking University Institutional Repository (PKU IR) |
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English |
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Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation. Previous energy-efficient approaches usually suffer from performance degradation and redundant extension bits. In this paper, we propose a Way History Oriented Low Energy Instruction Cache (WHOLE-Cache) design for single issue and in-order execution processors. The WHOLE-Cache design not only achieves a significant portion of energy reduction by effectively reducing dynamic energy dissipation of set-associative instruction cache, but also leads to no additional cycle penalties. Tag comparison results are stored into either the Branch Target Buffer (BTB) or the Instruction Cache (I-Cache) to avoid tag checks and unnecessary way activation for subsequent accesses to visited cache lines. The extended BTB uses way history bits for branch instructions, while the I-Cache extension bits are used in case of fetching consecutive instructions resided in different cache lines. A valid flag is associated with each stored tag comparison result to indicate whether the instruction to be fetched is resided in the recorded location. A simple invalidation scheme is implemented in the cache miss replacement operation. Whenever a cache line is replaced, the pointers to it, which reside in the BTB or other I-cache lines, will be invalidated accordingly. We model the WHOLE-Cache design in Verilog. By deriving basic parameters from TSMC 65nm technology, we use Wattch simulator to evaluate the performance and energy reduction of the WHOLE-Cache in the instruction fetch stage. We use SPEC2000 and Mediabench as benchmarks. It is observed that compared with a conventional 4-way set-associative I-Cache, the energy consumption of the WHOLE-Cache is reduced by 65% without any performance penalty. Computer Science, Hardware & Architecture Computer Science, Theory & Methods Engineering, Electrical & Electronic EI CPCI-S(ISTP) 1 |
author2 |
Xie, ZC (reprint author), Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China. Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China. |
format |
Conference Object |
author |
Xie, Zichao Tong, Dong Cheng, Xu |
spellingShingle |
Xie, Zichao Tong, Dong Cheng, Xu WHOLE: A Low Energy I-Cache with Separate Way History |
author_facet |
Xie, Zichao Tong, Dong Cheng, Xu |
author_sort |
Xie, Zichao |
title |
WHOLE: A Low Energy I-Cache with Separate Way History |
title_short |
WHOLE: A Low Energy I-Cache with Separate Way History |
title_full |
WHOLE: A Low Energy I-Cache with Separate Way History |
title_fullStr |
WHOLE: A Low Energy I-Cache with Separate Way History |
title_full_unstemmed |
WHOLE: A Low Energy I-Cache with Separate Way History |
title_sort |
whole: a low energy i-cache with separate way history |
publishDate |
2009 |
url |
https://hdl.handle.net/20.500.11897/260967 https://doi.org/10.1109/ICCD.2009.5413162 |
genre |
The Pointers |
genre_facet |
The Pointers |
op_source |
EI SCI |
op_relation |
2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN. 1057871 1063-6404 http://hdl.handle.net/20.500.11897/260967 doi:10.1109/ICCD.2009.5413162 WOS:000277251900022 |
op_doi |
https://doi.org/20.500.11897/260967 https://doi.org/10.1109/ICCD.2009.5413162 |
container_title |
2009 IEEE International Conference on Computer Design |
container_start_page |
137 |
op_container_end_page |
143 |
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1766216913758715904 |