Subthreshold Dual Mode Logic
In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power d...
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Universitas Ahmad Dahlan
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ftneliti:oai:neliti.com:54932 2023-05-15T16:01:16+02:00 Subthreshold Dual Mode Logic Reddy, J. N. (J) Sathyanarayana, T. (T) Khadar Baba, M.A 2014-06-01 application/pdf https://www.neliti.com/publications/54932/subthreshold-dual-mode-logic en eng Universitas Ahmad Dahlan https://www.neliti.com/publications/54932/subthreshold-dual-mode-logic (c) Bulletin of Electrical Engineering and Informatics, 2014 Bulletin of Electrical Engineering and Informatics Indonesia Journal:eArticle 2014 ftneliti 2022-10-19T01:25:09Z In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept. Other/Unknown Material DML neliti (Indonesia's Think Tank Database) |
institution |
Open Polar |
collection |
neliti (Indonesia's Think Tank Database) |
op_collection_id |
ftneliti |
language |
English |
topic |
Indonesia |
spellingShingle |
Indonesia Reddy, J. N. (J) Sathyanarayana, T. (T) Khadar Baba, M.A Subthreshold Dual Mode Logic |
topic_facet |
Indonesia |
description |
In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept. |
format |
Other/Unknown Material |
author |
Reddy, J. N. (J) Sathyanarayana, T. (T) Khadar Baba, M.A |
author_facet |
Reddy, J. N. (J) Sathyanarayana, T. (T) Khadar Baba, M.A |
author_sort |
Reddy, J. N. (J) |
title |
Subthreshold Dual Mode Logic |
title_short |
Subthreshold Dual Mode Logic |
title_full |
Subthreshold Dual Mode Logic |
title_fullStr |
Subthreshold Dual Mode Logic |
title_full_unstemmed |
Subthreshold Dual Mode Logic |
title_sort |
subthreshold dual mode logic |
publisher |
Universitas Ahmad Dahlan |
publishDate |
2014 |
url |
https://www.neliti.com/publications/54932/subthreshold-dual-mode-logic |
genre |
DML |
genre_facet |
DML |
op_source |
Bulletin of Electrical Engineering and Informatics |
op_relation |
https://www.neliti.com/publications/54932/subthreshold-dual-mode-logic |
op_rights |
(c) Bulletin of Electrical Engineering and Informatics, 2014 |
_version_ |
1766397205989556224 |