Technology mapping for FPGAs with composite logic block architectures
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts....
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ftnctuniv:oai:ir.nctu.edu.tw:11536/149341 2023-05-15T17:53:34+02:00 Technology mapping for FPGAs with composite logic block architectures Chuang, HH Shung, CB 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics 1996-10-01 http://hdl.handle.net/11536/149341 en_US eng 0916-8532 http://hdl.handle.net/11536/149341 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS WOS:A1996VP06900005 technology mapping FPGA subject graph pattern graph Article 1996 ftnctuniv 2019-04-05T00:09:51Z A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results. Article in Journal/Newspaper Orca National Chiao Tung University: NCTU Institutional Repository |
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Open Polar |
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National Chiao Tung University: NCTU Institutional Repository |
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ftnctuniv |
language |
English |
topic |
technology mapping FPGA subject graph pattern graph |
spellingShingle |
technology mapping FPGA subject graph pattern graph Chuang, HH Shung, CB Technology mapping for FPGAs with composite logic block architectures |
topic_facet |
technology mapping FPGA subject graph pattern graph |
description |
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results. |
author2 |
電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
format |
Article in Journal/Newspaper |
author |
Chuang, HH Shung, CB |
author_facet |
Chuang, HH Shung, CB |
author_sort |
Chuang, HH |
title |
Technology mapping for FPGAs with composite logic block architectures |
title_short |
Technology mapping for FPGAs with composite logic block architectures |
title_full |
Technology mapping for FPGAs with composite logic block architectures |
title_fullStr |
Technology mapping for FPGAs with composite logic block architectures |
title_full_unstemmed |
Technology mapping for FPGAs with composite logic block architectures |
title_sort |
technology mapping for fpgas with composite logic block architectures |
publishDate |
1996 |
url |
http://hdl.handle.net/11536/149341 |
genre |
Orca |
genre_facet |
Orca |
op_relation |
0916-8532 http://hdl.handle.net/11536/149341 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS WOS:A1996VP06900005 |
_version_ |
1766161279168282624 |