Low power dual mode CMOS logic

• Main Author: Lei, Yuze
• Other Authors: Lau Kim Teen, School of Electrical and Electronic Engineering
• Format: Other/Unknown Material
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering; The Gate; DML
• Online Access: http://hdl.handle.net/10356/61339

The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of...