Low power dual mode CMOS logic
The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of...
Main Author: | |
---|---|
Other Authors: | , |
Format: | Other/Unknown Material |
Language: | English |
Published: |
2014
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/61339 |
id |
ftnanyangtu:oai:dr.ntu.edu.sg:10356/61339 |
---|---|
record_format |
openpolar |
spelling |
ftnanyangtu:oai:dr.ntu.edu.sg:10356/61339 2023-07-30T04:03:11+02:00 Low power dual mode CMOS logic Lei, Yuze Lau Kim Teen School of Electrical and Electronic Engineering 2014 51 p. application/pdf http://hdl.handle.net/10356/61339 en eng http://hdl.handle.net/10356/61339 Nanyang Technological University DRNTU::Engineering::Electrical and electronic engineering Final Year Project (FYP) 2014 ftnanyangtu 2023-07-14T00:23:33Z The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance,however, it is accompanied with increased power dissipation. This is achieved with a simple and intuitive design concept.I use the software “Cadence” to compare performance, power dissipation, and speed of the presented DML gates to their CMOS and domino.The DML gates,CMOS and domino what have been mentioned above are all consisted of the NAND gate in this paper. Bachelor of Engineering Other/Unknown Material DML DR-NTU (Digital Repository at Nanyang Technological University, Singapore) The Gate ENVELOPE(-124.937,-124.937,61.417,61.417) |
institution |
Open Polar |
collection |
DR-NTU (Digital Repository at Nanyang Technological University, Singapore) |
op_collection_id |
ftnanyangtu |
language |
English |
topic |
DRNTU::Engineering::Electrical and electronic engineering |
spellingShingle |
DRNTU::Engineering::Electrical and electronic engineering Lei, Yuze Low power dual mode CMOS logic |
topic_facet |
DRNTU::Engineering::Electrical and electronic engineering |
description |
The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance,however, it is accompanied with increased power dissipation. This is achieved with a simple and intuitive design concept.I use the software “Cadence” to compare performance, power dissipation, and speed of the presented DML gates to their CMOS and domino.The DML gates,CMOS and domino what have been mentioned above are all consisted of the NAND gate in this paper. Bachelor of Engineering |
author2 |
Lau Kim Teen School of Electrical and Electronic Engineering |
format |
Other/Unknown Material |
author |
Lei, Yuze |
author_facet |
Lei, Yuze |
author_sort |
Lei, Yuze |
title |
Low power dual mode CMOS logic |
title_short |
Low power dual mode CMOS logic |
title_full |
Low power dual mode CMOS logic |
title_fullStr |
Low power dual mode CMOS logic |
title_full_unstemmed |
Low power dual mode CMOS logic |
title_sort |
low power dual mode cmos logic |
publishDate |
2014 |
url |
http://hdl.handle.net/10356/61339 |
long_lat |
ENVELOPE(-124.937,-124.937,61.417,61.417) |
geographic |
The Gate |
geographic_facet |
The Gate |
genre |
DML |
genre_facet |
DML |
op_relation |
http://hdl.handle.net/10356/61339 |
op_rights |
Nanyang Technological University |
_version_ |
1772814119596982272 |