Hardware implementation of a pipelined turbo decoder

• Main Author: Wang, Guan, 1973-
• Other Authors: Memorial University of Newfoundland. Faculty of Engineering and Applied Science
• Format: Thesis
• Language: English
• Published: 2010
• Subjects: Decoders (Electronics) > Design and construction; Error-correcting codes (Information theory); Monte Carlo method; VHDL (Computer hardware description language); Newfoundland studies; University of Newfoundland
• Online Access: http://collections.mun.ca/cdm/ref/collection/theses4/id/59112

Thesis (M.Eng.)--Memorial University of Newfoundland, 2010. Engineering and Applied Science Includes bibliographical references (leaves 91-94) Turbo codes have been widely studied since they were first proposed in 1993 by Berrou, Glavieux, and Thitimajshima in "Near Shannon Limit error-correcting coding and decoding: Turbo-codes" [1]. They have the advantage of providing a low bit error rate (BER) in decoding, and outperform linear block and convolutional codes in low signal-to-noise-ratio (SNR) environments. The decoding performance of turbo codes can be very close to the Shannon Limit, about 0.7decibel (dB). It is determined by the architectures of the constituent encoders and interleaver, but is bounded in high SNRs by an error floor. Turbo codes are widely used in communications. We explore the codeword weight spectrum properties that contribute to their excellent performance. Furthermore, the decoding performance is analyzed and compared with the free distance asymptotic performance. A 16-state turbo decoder is implemented using VHSIC Hardware Description Language (VHDL) and then mapped onto a field-programmable gate array (FPGA) board. The hardware implementations are compared with the software simulations to verify the decoding correctness. A pipelined architecture is then implemented which significantly reduces the decoding latency