Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism...
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ftmdpi:oai:mdpi.com:/2079-9292/10/9/1052/ 2023-08-20T04:06:10+02:00 Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco 2021-04-29 application/pdf https://doi.org/10.3390/electronics10091052 EN eng Multidisciplinary Digital Publishing Institute Circuit and Signal Processing https://dx.doi.org/10.3390/electronics10091052 https://creativecommons.org/licenses/by/4.0/ Electronics; Volume 10; Issue 9; Pages: 1052 address decoder controller Dual Mode Logic self-adaptive Text 2021 ftmdpi https://doi.org/10.3390/electronics10091052 2023-08-01T01:37:06Z This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. Text DML MDPI Open Access Publishing Electronics 10 9 1052 |
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MDPI Open Access Publishing |
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language |
English |
topic |
address decoder controller Dual Mode Logic self-adaptive |
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address decoder controller Dual Mode Logic self-adaptive Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
topic_facet |
address decoder controller Dual Mode Logic self-adaptive |
description |
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. |
format |
Text |
author |
Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco |
author_facet |
Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco |
author_sort |
Kevin Vicuña |
title |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_short |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_fullStr |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full_unstemmed |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_sort |
energy efficient self-adaptive dual mode logic address decoder |
publisher |
Multidisciplinary Digital Publishing Institute |
publishDate |
2021 |
url |
https://doi.org/10.3390/electronics10091052 |
genre |
DML |
genre_facet |
DML |
op_source |
Electronics; Volume 10; Issue 9; Pages: 1052 |
op_relation |
Circuit and Signal Processing https://dx.doi.org/10.3390/electronics10091052 |
op_rights |
https://creativecommons.org/licenses/by/4.0/ |
op_doi |
https://doi.org/10.3390/electronics10091052 |
container_title |
Electronics |
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10 |
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9 |
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1052 |
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1774717098740678656 |