Analysis of High-Performance Near-threshold Dual Mode Logic design

• Main Author: Bikki, Pavankumar
• Other Authors: NO
• Format: Article in Journal/Newspaper
• Language: English
• Published: Electronics and Telecommunications Committee 2019
• Subjects: CMOS logic; dual mode logic; dynamic mode; high performance; minimum energy point; near-threshold; DML
• Online Access: http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253

A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of sub-threshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.