Analysis of High-Performance Near-threshold Dual Mode Logic design
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation wi...
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Electronics and Telecommunications Committee
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ftjijet:oai:ojs.ijet.ise.pw.edu.pl:article/1845 2023-07-30T04:03:11+02:00 Analysis of High-Performance Near-threshold Dual Mode Logic design Bikki, Pavankumar NO 2019-10-07 application/pdf http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253 eng eng Electronics and Telecommunications Committee http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253/633 http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130253/1448 http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253 Copyright (c) 2019 International Journal of Electronics and Telecommunications International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 723-729 2300-1933 CMOS logic dual mode logic dynamic mode high performance minimum energy point near-threshold info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion 2019 ftjijet 2023-07-12T07:08:35Z A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of sub-threshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance. Article in Journal/Newspaper DML International Journal of Electronics and Telecommunications (Warsaw University of Technology) |
institution |
Open Polar |
collection |
International Journal of Electronics and Telecommunications (Warsaw University of Technology) |
op_collection_id |
ftjijet |
language |
English |
topic |
CMOS logic dual mode logic dynamic mode high performance minimum energy point near-threshold |
spellingShingle |
CMOS logic dual mode logic dynamic mode high performance minimum energy point near-threshold Bikki, Pavankumar Analysis of High-Performance Near-threshold Dual Mode Logic design |
topic_facet |
CMOS logic dual mode logic dynamic mode high performance minimum energy point near-threshold |
description |
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of sub-threshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance. |
author2 |
NO |
format |
Article in Journal/Newspaper |
author |
Bikki, Pavankumar |
author_facet |
Bikki, Pavankumar |
author_sort |
Bikki, Pavankumar |
title |
Analysis of High-Performance Near-threshold Dual Mode Logic design |
title_short |
Analysis of High-Performance Near-threshold Dual Mode Logic design |
title_full |
Analysis of High-Performance Near-threshold Dual Mode Logic design |
title_fullStr |
Analysis of High-Performance Near-threshold Dual Mode Logic design |
title_full_unstemmed |
Analysis of High-Performance Near-threshold Dual Mode Logic design |
title_sort |
analysis of high-performance near-threshold dual mode logic design |
publisher |
Electronics and Telecommunications Committee |
publishDate |
2019 |
url |
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253 |
genre |
DML |
genre_facet |
DML |
op_source |
International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 723-729 2300-1933 |
op_relation |
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253/633 http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130253/1448 http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130253 |
op_rights |
Copyright (c) 2019 International Journal of Electronics and Telecommunications |
_version_ |
1772814117903532032 |