Synthesis of Dual Mode Logic

• Published in: Integration
• Main Authors: Moyal, Lior, Levi, Itamar, Teman, Adam, Fish, Alexander
• Format: Text
• Language: unknown
• Published: Amsterdam, Elsevier 2016
• Subjects: DML
• Online Access: https://doi.org/10.1016/j.vlsi.2016.07.004; http://infoscience.epfl.ch/record/223296

In recent years, the major focus of VLSI design has shifted from high-speed to low-power consumption. While standard CMOS-based digital design provides substantial flexibility during pre-silicon design phases, the characteristics of the gates are set by fabrication variations and environmental conditions and cannot easily be changed at runtime. The recently proposed Dual Mode Logic (DML) family provides a novel approach to provide this capability by introducing two configurable operating modes, static and dynamic, that enable fine-grained control of the power-performance tradeoff of a logic path. However, the introduction of a new topology requires the development of both a design methodology and techniques for integration in a robust design automation flow. Standard synthesis tools do not support dynamic gates, and in particular, dual-characteristic gates. Therefore, until now, DML has been limited to small, custom-made blocks and components. In this paper, we present a novel approach for the integration of DML into standard electronic design automation tools, as part of the standard digital design flow. The development of this approach and the accompanying design methodology enables DML to be used in larger designs, such as state-of-the-art, high-speed and/or low-power SoCs. We demonstrate the employment of the proposed approach in order to benefit from DML properties, and reduce the power consumption, while simultaneously improving the operating frequency of a number of test designs. (C) 2016 Elsevier Ltd. All rights reserved.