Toward Wafer-Scale Screening of Spin Qubits: A Room-Temperature-Aware Single-Electron Transistor Design

• Published in: IEEE Transactions on Electron Devices
• Main Authors: Lorenzelli, Francesco, Chen, Kuan-Chu, Godfrin, Clement, Stucchi, Michele, Grill, Alexander, Wan, Danny, De Greve, Kristiaan, Marinissen, Erik Jan, Gielen, Georges
• Format: Article in Journal/Newspaper
• Language: English
• Published: Institute of Electrical and Electronics Engineers 2025
• Subjects: Cryogenic temperature; Cryogenics; Electrons; electron-spin qubit; Electrostatics; Engineering; Electrical & Electronic; FREEZE-OUT; Logic gates; Measurement; Performance evaluation; Physical Sciences; Physics; Applied; QUANTUM; quantum computing; Quantum dots; Qubit; room temperature; Science & Technology; single-electron transistor (SET); Technology; technology computer-aided design (TCAD) simulation; Transistors; Tunneling; 0906 Electrical and Electronic Engineering; Applied Physics; 4009 Electronics; sensors and digital hardware; Arctic
• Online Access: https://lirias.kuleuven.be/handle/20.500.12942/770072; https://hdl.handle.net/20.500.12942/770072; https://doi.org/10.1109/TED.2025.3578553

Testing of spin-based quantum devices is currently performed through quantum dot and qubit measurements at deep cryogenic temperatures, well below 1 K. At such low temperatures, the testing throughput is strongly limited due to the long cool-down times and due to the large number of connections required between the device at deep-cryogenic temperature and the room-temperature control electronics. As the number of qubits in a single chip increases and as we advance toward large-scale manufacturing, developing effective techniques that allow to screen those chips at higher temperatures, possibly even room temperature, becomes indispensable. Transistor metrics constitute a promising indicator to identify, at room temperature, which devices are functional and also at cryogenic temperatures. Prior work has demonstrated a strong correlation between quantum dot metrics measured at deep-cryogenic temperature and transistor metrics up to 77 K. To ensure that such a correlation extends up to room temperature, electrostatic confinement of the conductive channel needs to be guaranteed. In this article, we propose a single-electron transistor (SET) design intended for the correlation study of transistor metrics from deep-cryogenic up to room temperatures. Our calibrated technology computer-aided design (TCAD) simulation results demonstrate the drastic improvement of the room-temperature transistor behavior of the proposed design, without the employment of physical device isolation that would negatively impact the qubit’s fidelity. In addition, this work presents a room-temperature-aware methodology in the design phase of spin-based devices, with promising scalability to structures containing a larger number of qubits. sponsorship: This work was supported in part by the Chips Joint Undertaking Project Advanced Research on Cryogenic Technologies for Innovative Computing (ARCTIC) under Project 101139908; in part by the Chips JU and Its Members (Including Top-Up Funding by Belgium, Austria, Germany, Estonia, Finland, France, ...