Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic

• Main Author: M.R.Sangameswari
• Format: Article in Journal/Newspaper
• Language: English
• Published: International Journal of Computer Science and Engineering Communications 2015
• Subjects: VLSI; flip flops; power dissipation; split dynamic nodes; DDFF-ELM; DML; Flop
• Online Access: http://www.hindex.org/2015/article.php?page=104

Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introduced here. Both of them eliminate the drawbacks of existing h...