Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic
Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introduced here. Both of them eliminate the drawbacks of existing h...
| Main Author: | |
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| Format: | Article in Journal/Newspaper |
| Language: | English |
| Published: |
International Journal of Computer Science and Engineering Communications
2015
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| Subjects: | |
| Online Access: | http://www.hindex.org/2015/article.php?page=104 |
| _version_ | 1821499193547554816 |
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| author | M.R.Sangameswari |
| author2 | M.R.Sangameswari |
| author_facet | M.R.Sangameswari |
| author_sort | M.R.Sangameswari |
| collection | SCIA - Scholarly Citation Index Analytics |
| description | Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introduced here. Both of them eliminate the drawbacks of existing high performance flip-flop designs. |
| format | Article in Journal/Newspaper |
| genre | DML |
| genre_facet | DML |
| geographic | Flop |
| geographic_facet | Flop |
| id | fthindex:oai:hindex.org/2015/article.php-page-104 |
| institution | Open Polar |
| language | English |
| long_lat | ENVELOPE(-56.753,-56.753,-61.028,-61.028) |
| op_collection_id | fthindex |
| op_relation | http://www.hindex.org/2015/article.php?page=104 |
| op_rights | Creative Commons Attribution 4.0 International License |
| op_rightsnorm | CC-BY |
| publishDate | 2015 |
| publisher | International Journal of Computer Science and Engineering Communications |
| record_format | openpolar |
| spelling | fthindex:oai:hindex.org/2015/article.php-page-104 2025-01-16T21:38:35+00:00 Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic M.R.Sangameswari M.R.Sangameswari 2015-04-25 Application/pdf http://www.hindex.org/2015/article.php?page=104 Eng eng International Journal of Computer Science and Engineering Communications http://www.hindex.org/2015/article.php?page=104 Creative Commons Attribution 4.0 International License CC-BY VLSI flip flops power dissipation split dynamic nodes DDFF-ELM DML Article 2015 fthindex 2020-03-14T16:11:23Z Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introduced here. Both of them eliminate the drawbacks of existing high performance flip-flop designs. Article in Journal/Newspaper DML SCIA - Scholarly Citation Index Analytics Flop ENVELOPE(-56.753,-56.753,-61.028,-61.028) |
| spellingShingle | VLSI flip flops power dissipation split dynamic nodes DDFF-ELM DML M.R.Sangameswari Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title | Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title_full | Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title_fullStr | Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title_full_unstemmed | Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title_short | Low Power Design of Johnson Counter Using DDFF Featuring Dual Mode Logic |
| title_sort | low power design of johnson counter using ddff featuring dual mode logic |
| topic | VLSI flip flops power dissipation split dynamic nodes DDFF-ELM DML |
| topic_facet | VLSI flip flops power dissipation split dynamic nodes DDFF-ELM DML |
| url | http://www.hindex.org/2015/article.php?page=104 |