Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism...
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2021
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ftdoajarticles:oai:doaj.org/article:53c39305fa744122998dc716122e5ddf 2023-05-15T16:02:00+02:00 Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco 2021-04-01T00:00:00Z https://doi.org/10.3390/electronics10091052 https://doaj.org/article/53c39305fa744122998dc716122e5ddf EN eng MDPI AG https://www.mdpi.com/2079-9292/10/9/1052 https://doaj.org/toc/2079-9292 doi:10.3390/electronics10091052 2079-9292 https://doaj.org/article/53c39305fa744122998dc716122e5ddf Electronics, Vol 10, Iss 1052, p 1052 (2021) address decoder controller Dual Mode Logic self-adaptive Electronics TK7800-8360 article 2021 ftdoajarticles https://doi.org/10.3390/electronics10091052 2022-12-30T21:09:52Z This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. Article in Journal/Newspaper DML Directory of Open Access Journals: DOAJ Articles Electronics 10 9 1052 |
institution |
Open Polar |
collection |
Directory of Open Access Journals: DOAJ Articles |
op_collection_id |
ftdoajarticles |
language |
English |
topic |
address decoder controller Dual Mode Logic self-adaptive Electronics TK7800-8360 |
spellingShingle |
address decoder controller Dual Mode Logic self-adaptive Electronics TK7800-8360 Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
topic_facet |
address decoder controller Dual Mode Logic self-adaptive Electronics TK7800-8360 |
description |
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode. |
format |
Article in Journal/Newspaper |
author |
Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco |
author_facet |
Kevin Vicuña Cristhopher Mosquera Ariana Musello Sara Benedictis Mateo Rendón Esteban Garzón Luis Miguel Prócel Lionel Trojman Ramiro Taco |
author_sort |
Kevin Vicuña |
title |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_short |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_fullStr |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_full_unstemmed |
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder |
title_sort |
energy efficient self-adaptive dual mode logic address decoder |
publisher |
MDPI AG |
publishDate |
2021 |
url |
https://doi.org/10.3390/electronics10091052 https://doaj.org/article/53c39305fa744122998dc716122e5ddf |
genre |
DML |
genre_facet |
DML |
op_source |
Electronics, Vol 10, Iss 1052, p 1052 (2021) |
op_relation |
https://www.mdpi.com/2079-9292/10/9/1052 https://doaj.org/toc/2079-9292 doi:10.3390/electronics10091052 2079-9292 https://doaj.org/article/53c39305fa744122998dc716122e5ddf |
op_doi |
https://doi.org/10.3390/electronics10091052 |
container_title |
Electronics |
container_volume |
10 |
container_issue |
9 |
container_start_page |
1052 |
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1766397649497358336 |