Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs
Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the uttermost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximiz...
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ftdatacite:10.48550/arxiv.2101.01745 2023-05-15T17:25:06+02:00 Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs Hogervorst, Tom Qiu, Tong Dong Marchiori, Giacomo Birger, Alf Blatt, Markus Nane, Razvan 2021 https://dx.doi.org/10.48550/arxiv.2101.01745 https://arxiv.org/abs/2101.01745 unknown arXiv https://dx.doi.org/10.1145/3476229 arXiv.org perpetual, non-exclusive license http://arxiv.org/licenses/nonexclusive-distrib/1.0/ Hardware Architecture cs.AR Computational Physics physics.comp-ph FOS Computer and information sciences FOS Physical sciences article-journal Article ScholarlyArticle Text 2021 ftdatacite https://doi.org/10.48550/arxiv.2101.01745 https://doi.org/10.1145/3476229 2022-03-10T15:01:19Z Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the uttermost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. A Field-Programmable Gate Array is a reconfigurable hardware accelerator that is fully customizable in terms of computational resources and memory storage requirements of an application during its lifetime. Therefore, it is an ideal candidate to accelerate scientific computing applications because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers found in scientific libraries. In this paper, we study the potential of using FPGA in HPC because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we first propose a novel ILU0 preconditioner tightly integrated with a BiCGStab solver kernel designed using a mixture of High-Level Synthesis and Register-Transfer Level hand-coded design. Second, we integrate the developed preconditioned iterative solver in Flow from the Open Porous Media (OPM) project, a state-of-the-art open-source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both standalone mode and integrated into the reservoir simulator that includes all the on-chip URAM and BRAM, on-board High-Bandwidth Memory, and off-chip CPU memory data transfers required in a complex simulator software such as OPM's Flow. We evaluate the performance on the Norne field, a real-world case reservoir model using a grid with more than 10^5 cells and using 3 unknowns per cell. Article in Journal/Newspaper Norne field DataCite Metadata Store (German National Library of Science and Technology) |
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DataCite Metadata Store (German National Library of Science and Technology) |
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topic |
Hardware Architecture cs.AR Computational Physics physics.comp-ph FOS Computer and information sciences FOS Physical sciences |
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Hardware Architecture cs.AR Computational Physics physics.comp-ph FOS Computer and information sciences FOS Physical sciences Hogervorst, Tom Qiu, Tong Dong Marchiori, Giacomo Birger, Alf Blatt, Markus Nane, Razvan Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
topic_facet |
Hardware Architecture cs.AR Computational Physics physics.comp-ph FOS Computer and information sciences FOS Physical sciences |
description |
Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the uttermost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. A Field-Programmable Gate Array is a reconfigurable hardware accelerator that is fully customizable in terms of computational resources and memory storage requirements of an application during its lifetime. Therefore, it is an ideal candidate to accelerate scientific computing applications because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers found in scientific libraries. In this paper, we study the potential of using FPGA in HPC because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we first propose a novel ILU0 preconditioner tightly integrated with a BiCGStab solver kernel designed using a mixture of High-Level Synthesis and Register-Transfer Level hand-coded design. Second, we integrate the developed preconditioned iterative solver in Flow from the Open Porous Media (OPM) project, a state-of-the-art open-source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both standalone mode and integrated into the reservoir simulator that includes all the on-chip URAM and BRAM, on-board High-Bandwidth Memory, and off-chip CPU memory data transfers required in a complex simulator software such as OPM's Flow. We evaluate the performance on the Norne field, a real-world case reservoir model using a grid with more than 10^5 cells and using 3 unknowns per cell. |
format |
Article in Journal/Newspaper |
author |
Hogervorst, Tom Qiu, Tong Dong Marchiori, Giacomo Birger, Alf Blatt, Markus Nane, Razvan |
author_facet |
Hogervorst, Tom Qiu, Tong Dong Marchiori, Giacomo Birger, Alf Blatt, Markus Nane, Razvan |
author_sort |
Hogervorst, Tom |
title |
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
title_short |
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
title_full |
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
title_fullStr |
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
title_full_unstemmed |
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs |
title_sort |
hardware acceleration of hpc computational flow dynamics using hbm-enabled fpgas |
publisher |
arXiv |
publishDate |
2021 |
url |
https://dx.doi.org/10.48550/arxiv.2101.01745 https://arxiv.org/abs/2101.01745 |
genre |
Norne field |
genre_facet |
Norne field |
op_relation |
https://dx.doi.org/10.1145/3476229 |
op_rights |
arXiv.org perpetual, non-exclusive license http://arxiv.org/licenses/nonexclusive-distrib/1.0/ |
op_doi |
https://doi.org/10.48550/arxiv.2101.01745 https://doi.org/10.1145/3476229 |
_version_ |
1766116397267550208 |