Constrained Random Test Environment for SoC Verification using VERA

• Main Authors: Victor Besyakov, David Shleifman
• Other Authors: The Pennsylvania State University CiteSeerX Archives
• Format: Text
• Language: English
• Published: 2002
• Subjects: Tundra
• Online Access: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.83.6803; http://www.open-vera.com/technical/constrained_tundra.pdf

Tundra Semiconductor is creating the next generation of system interconnect designs. Our typical design supports 10 buses, with at least four of the buses having different protocols. All of the buses map many different transactions from a one bus to another bus. In system verification, every block of the design must undergo detailed block level verification. Because of the complexity of the designs and the amount of resource and time associated with verification efforts it is almost impossible to complete 100 % functional coverage. However, if the functional verification is targeted to three to five typical applications where the device is going to be used, then the desired coverage is reduced which also reduces verification time. In this document, we describe the criteria to effectively exercise multiprotocol traffic. Based on these criteria we demonstrate how to assert hierarchal constraints in order to reproduce “real world” traffic. Finally, we describe System Scenario Generator (SSG) that implements these hierarchal constraints. The SSG is scalable to support any number of buses of the same type, is expandable to accommodate buses with new protocols, and is adjustable to incrementally shift