to Incremental Routing for ECO Applications in FPGAs

this article, we develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). The basic B&R idea (which was originally proposed in Dutt et al. [1999] in the much simpler context of extending some nets by a segment for the purpose of fault t...

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Main Authors: In Fpgas, Shantanu Dutt Vinay, Vinay Verma, Hasan Arslan
Other Authors: The Pennsylvania State University CiteSeerX Archives
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Language:English
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Online Access:http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.1109
http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf
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spelling ftciteseerx:oai:CiteSeerX.psu:10.1.1.7.1109 2023-05-15T17:53:33+02:00 to Incremental Routing for ECO Applications in FPGAs In Fpgas Shantanu Dutt Vinay Vinay Verma Hasan Arslan The Pennsylvania State University CiteSeerX Archives application/pdf http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.1109 http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf en eng http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.1109 http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf Metadata may be used without restrictions as long as the oai identifier remains attached to it. http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf text ftciteseerx 2016-01-08T18:48:45Z this article, we develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). The basic B&R idea (which was originally proposed in Dutt et al. [1999] in the much simpler context of extending some nets by a segment for the purpose of fault tolerance) in our algorithms is to rearrange some portions of some existing nets on other tracks within their current channels in order to find valid routings for the new/modified nets without requiring any extra routing resources and with little effect on the electrical properties of existing nets. Here we significantly extend the B&R concept to global and detailed incremental routing for FPGAs with complex switchboxes (SBox's) such as those in Lucent's ORCA and Xilinx's Virtex series. We introduce new concepts such as a B&R cost in global routing and the optimal subnet set to relocate for each bumped net (determined using an efficient dynamic programming formulation). We developed optimal and nearoptimal algorithms (called Subsec B&R and Subnet B&R, respectively) to find incremental routing solutions using the B&R paradigm in complex FPGAs (e.g., Lucent's ORCA FPGA) with i-to- j SBox's, as well as an optimal version Fullnet B&R for the VPR architecture from the University of Toronto using the simpler i-to-i SBox's. We compared our algorithms (simply called B&R when no distinction needs to be made between our versions) to two recent incremental routing techniques, Standard (Std) and Rip-up&Reroute (R&R), and to Lucent's A PAR routing tool and the University of Toronto's VPR router used in complete rerouting modes. Experimental results for the ORCA show that B&R is 10 to 20 times faster than complete rerouting using A PAR, and that B&R is also nearly 27% faster and yields new nets w. Text Orca Unknown
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description this article, we develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). The basic B&R idea (which was originally proposed in Dutt et al. [1999] in the much simpler context of extending some nets by a segment for the purpose of fault tolerance) in our algorithms is to rearrange some portions of some existing nets on other tracks within their current channels in order to find valid routings for the new/modified nets without requiring any extra routing resources and with little effect on the electrical properties of existing nets. Here we significantly extend the B&R concept to global and detailed incremental routing for FPGAs with complex switchboxes (SBox's) such as those in Lucent's ORCA and Xilinx's Virtex series. We introduce new concepts such as a B&R cost in global routing and the optimal subnet set to relocate for each bumped net (determined using an efficient dynamic programming formulation). We developed optimal and nearoptimal algorithms (called Subsec B&R and Subnet B&R, respectively) to find incremental routing solutions using the B&R paradigm in complex FPGAs (e.g., Lucent's ORCA FPGA) with i-to- j SBox's, as well as an optimal version Fullnet B&R for the VPR architecture from the University of Toronto using the simpler i-to-i SBox's. We compared our algorithms (simply called B&R when no distinction needs to be made between our versions) to two recent incremental routing techniques, Standard (Std) and Rip-up&Reroute (R&R), and to Lucent's A PAR routing tool and the University of Toronto's VPR router used in complete rerouting modes. Experimental results for the ORCA show that B&R is 10 to 20 times faster than complete rerouting using A PAR, and that B&R is also nearly 27% faster and yields new nets w.
author2 The Pennsylvania State University CiteSeerX Archives
format Text
author In Fpgas
Shantanu Dutt Vinay
Vinay Verma
Hasan Arslan
spellingShingle In Fpgas
Shantanu Dutt Vinay
Vinay Verma
Hasan Arslan
to Incremental Routing for ECO Applications in FPGAs
author_facet In Fpgas
Shantanu Dutt Vinay
Vinay Verma
Hasan Arslan
author_sort In Fpgas
title to Incremental Routing for ECO Applications in FPGAs
title_short to Incremental Routing for ECO Applications in FPGAs
title_full to Incremental Routing for ECO Applications in FPGAs
title_fullStr to Incremental Routing for ECO Applications in FPGAs
title_full_unstemmed to Incremental Routing for ECO Applications in FPGAs
title_sort to incremental routing for eco applications in fpgas
url http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.1109
http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf
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http://www.ece.uic.edu/~dutt/././papers/todaes03-final.pdf
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