DESIGN OF SUBTHRESHOLD DML LOGIC GATES WITH POWER GATING TECHNIQUES

• Main Authors: Lakshmisree P V, Raghu M C
• Other Authors: The Pennsylvania State University CiteSeerX Archives
• Format: Text
• Language: English
• Subjects: Dual mode logic (DML; Subthreshold; DML
• Online Access: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.679.2814; http://ijret.org/Volumes/V03/I04/IJRET_110304032.pdf

Sub-threshold circuit design is one of the promising methods for low power to ultra-low power applications. Circuits which operate in the sub-threshold region use a supply voltage that is close to or less than the threshold voltages of the transistors, so that there is a significant reduction in both dynamic and static power consumption. The low-power dual mode logic (DML) family is a logic family designed to operate in the sub-threshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. The ability of DML circuits to operate in both the static and dynamic modes gives the opportunity to create efficient logic circuits which balance power consumption and operating frequency (speed of the circuit) requirements. In the static mode of operation, the dual mode logic gates has very low-power dissipation with moderate performance, and in the dynamic mode of operation they have higher performance, at the price of increased power dissipation