Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing
Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In thi...
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ftciteseerx:oai:CiteSeerX.psu:10.1.1.387.6329 2023-05-15T17:53:43+02:00 Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing Jai-ming Lin Song-ra Pan Yao-wen Chang The Pennsylvania State University CiteSeerX Archives application/pdf http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329 http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf en eng http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329 http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf Metadata may be used without restrictions as long as the oai identifier remains attached to it. http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf text ftciteseerx 2016-09-18T00:35:48Z Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6 % and 19.7 % improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively. 1 Text Orca Unknown |
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description |
Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6 % and 19.7 % improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively. 1 |
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The Pennsylvania State University CiteSeerX Archives |
format |
Text |
author |
Jai-ming Lin Song-ra Pan Yao-wen Chang |
spellingShingle |
Jai-ming Lin Song-ra Pan Yao-wen Chang Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
author_facet |
Jai-ming Lin Song-ra Pan Yao-wen Chang |
author_sort |
Jai-ming Lin |
title |
Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
title_short |
Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
title_full |
Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
title_fullStr |
Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
title_full_unstemmed |
Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing |
title_sort |
graph matching-based algorithms for array-based fpga segmentation design and routing |
url |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329 http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf |
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Orca |
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Orca |
op_source |
http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf |
op_relation |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329 http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf |
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Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
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1766161432952438784 |