Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing
Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In thi...
| Main Authors: | , , |
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| Format: | Text |
| Language: | English |
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| Online Access: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6329 http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/09b_5.pdf |
| Summary: | Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6 % and 19.7 % improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively. 1 |
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