REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection
International audience Cache side-channel attacks consist, for a malicious process, to infer the current state of the cache by measuring the time it takes to access the memory, and indirectly gain knowledge about other processes sharing this same physical cache. Because cache side-channel attacks le...
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ftccsdartic:oai:HAL:hal-02949624v1 2023-05-15T17:53:51+02:00 REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection Mao, Yuxiao Migliore, Vincent Nicomette, Vincent Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF) Laboratoire d'analyse et d'architecture des systèmes (LAAS) Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1) Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3) Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse) Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP) Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1) Université Fédérale Toulouse Midi-Pyrénées Genova, Italy 2020-09-07 https://hal.laas.fr/hal-02949624 https://hal.laas.fr/hal-02949624/document https://hal.laas.fr/hal-02949624/file/Mao%20et%20al.%20-%202020%20-%20REHAD%20Using%20Low-Frequency%20Reconfigurable%20Hardware.pdf https://doi.org/10.1109/EuroS&PW51379.2020.00100 en eng HAL CCSD info:eu-repo/semantics/altIdentifier/doi/10.1109/EuroS&PW51379.2020.00100 hal-02949624 https://hal.laas.fr/hal-02949624 https://hal.laas.fr/hal-02949624/document https://hal.laas.fr/hal-02949624/file/Mao%20et%20al.%20-%202020%20-%20REHAD%20Using%20Low-Frequency%20Reconfigurable%20Hardware.pdf doi:10.1109/EuroS&PW51379.2020.00100 info:eu-repo/semantics/OpenAccess 2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW) https://hal.laas.fr/hal-02949624 2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW), Sep 2020, Genova, Italy. ⟨10.1109/EuroS&PW51379.2020.00100⟩ https://www.ieee-security.org/TC/EuroSP2020/ Reconfigurable architecture Intrusion detetion Microarchitectural timing attacks RISC-V [INFO]Computer Science [cs] [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] info:eu-repo/semantics/conferenceObject Conference papers 2020 ftccsdartic https://doi.org/10.1109/EuroS&PW51379.2020.00100 https://doi.org/10.1109/EuroS 2021-11-07T00:44:12Z International audience Cache side-channel attacks consist, for a malicious process, to infer the current state of the cache by measuring the time it takes to access the memory, and indirectly gain knowledge about other processes sharing this same physical cache. Because cache side-channel attacks leverage a hardware leakage without requiring any physical access to the devices, they represent very serious threats. Among the runtime detection techniques for cache side-channel attacks, hardware solutions are usually fine-grained and benefit from less performance overhead than software solutions. However, they are not flexible enough to suit the rapid evolution and appearance of software attacks. In this paper we describe REHAD, a novel attack detection architecture that uses reconfigurable hardware. More precisely, it includes a hardware detection module that can be reconfigured by means of a trusted software kernel, to adapt to the level of threats and to detect new attacks. This architecture also benefits from hardware parallelism to fill the frequency gap between reconfigurable hardware and core processor. REHAD has been integrated into the ORCA softcore RISC-V on a FPGA and two common cache side-channel attacks have been successfully detected. Conference Object Orca Archive ouverte HAL (Hyper Article en Ligne, CCSD - Centre pour la Communication Scientifique Directe) Genova ENVELOPE(-82.713,-82.713,-79.863,-79.863) |
institution |
Open Polar |
collection |
Archive ouverte HAL (Hyper Article en Ligne, CCSD - Centre pour la Communication Scientifique Directe) |
op_collection_id |
ftccsdartic |
language |
English |
topic |
Reconfigurable architecture Intrusion detetion Microarchitectural timing attacks RISC-V [INFO]Computer Science [cs] [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] |
spellingShingle |
Reconfigurable architecture Intrusion detetion Microarchitectural timing attacks RISC-V [INFO]Computer Science [cs] [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] Mao, Yuxiao Migliore, Vincent Nicomette, Vincent REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
topic_facet |
Reconfigurable architecture Intrusion detetion Microarchitectural timing attacks RISC-V [INFO]Computer Science [cs] [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] |
description |
International audience Cache side-channel attacks consist, for a malicious process, to infer the current state of the cache by measuring the time it takes to access the memory, and indirectly gain knowledge about other processes sharing this same physical cache. Because cache side-channel attacks leverage a hardware leakage without requiring any physical access to the devices, they represent very serious threats. Among the runtime detection techniques for cache side-channel attacks, hardware solutions are usually fine-grained and benefit from less performance overhead than software solutions. However, they are not flexible enough to suit the rapid evolution and appearance of software attacks. In this paper we describe REHAD, a novel attack detection architecture that uses reconfigurable hardware. More precisely, it includes a hardware detection module that can be reconfigured by means of a trusted software kernel, to adapt to the level of threats and to detect new attacks. This architecture also benefits from hardware parallelism to fill the frequency gap between reconfigurable hardware and core processor. REHAD has been integrated into the ORCA softcore RISC-V on a FPGA and two common cache side-channel attacks have been successfully detected. |
author2 |
Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF) Laboratoire d'analyse et d'architecture des systèmes (LAAS) Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1) Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3) Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse) Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP) Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1) Université Fédérale Toulouse Midi-Pyrénées |
format |
Conference Object |
author |
Mao, Yuxiao Migliore, Vincent Nicomette, Vincent |
author_facet |
Mao, Yuxiao Migliore, Vincent Nicomette, Vincent |
author_sort |
Mao, Yuxiao |
title |
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
title_short |
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
title_full |
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
title_fullStr |
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
title_full_unstemmed |
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection |
title_sort |
rehad: using low-frequency reconfigurable hardware for cache side-channel attacks detection |
publisher |
HAL CCSD |
publishDate |
2020 |
url |
https://hal.laas.fr/hal-02949624 https://hal.laas.fr/hal-02949624/document https://hal.laas.fr/hal-02949624/file/Mao%20et%20al.%20-%202020%20-%20REHAD%20Using%20Low-Frequency%20Reconfigurable%20Hardware.pdf https://doi.org/10.1109/EuroS&PW51379.2020.00100 |
op_coverage |
Genova, Italy |
long_lat |
ENVELOPE(-82.713,-82.713,-79.863,-79.863) |
geographic |
Genova |
geographic_facet |
Genova |
genre |
Orca |
genre_facet |
Orca |
op_source |
2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW) https://hal.laas.fr/hal-02949624 2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW), Sep 2020, Genova, Italy. ⟨10.1109/EuroS&PW51379.2020.00100⟩ https://www.ieee-security.org/TC/EuroSP2020/ |
op_relation |
info:eu-repo/semantics/altIdentifier/doi/10.1109/EuroS&PW51379.2020.00100 hal-02949624 https://hal.laas.fr/hal-02949624 https://hal.laas.fr/hal-02949624/document https://hal.laas.fr/hal-02949624/file/Mao%20et%20al.%20-%202020%20-%20REHAD%20Using%20Low-Frequency%20Reconfigurable%20Hardware.pdf doi:10.1109/EuroS&PW51379.2020.00100 |
op_rights |
info:eu-repo/semantics/OpenAccess |
op_doi |
https://doi.org/10.1109/EuroS&PW51379.2020.00100 https://doi.org/10.1109/EuroS |
_version_ |
1766161545203548160 |