Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor

Bibliographic Details
Published in:2015 IEEE East-West Design & Test Symposium (EWDTS)
Main Authors: Melikyan, Vazgen, Babayan, Eduard, Melikyan, Anush, Babayan, Davit, Petrosyan, Poghos, Mkrtchyan, Edvard
Format: Conference Object
Language:unknown
Published: IEEE 2015
Subjects:
Orca
Online Access:http://dx.doi.org/10.1109/ewdts.2015.7493159
http://xplorestaging.ieee.org/ielx7/7488713/7493093/07493159.pdf?arnumber=7493159
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spelling crieeecr:10.1109/ewdts.2015.7493159 2024-06-23T07:55:57+00:00 Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor Melikyan, Vazgen Babayan, Eduard Melikyan, Anush Babayan, Davit Petrosyan, Poghos Mkrtchyan, Edvard 2015 http://dx.doi.org/10.1109/ewdts.2015.7493159 http://xplorestaging.ieee.org/ielx7/7488713/7493093/07493159.pdf?arnumber=7493159 unknown IEEE 2015 IEEE East-West Design & Test Symposium (EWDTS) proceedings-article 2015 crieeecr https://doi.org/10.1109/ewdts.2015.7493159 2024-06-10T04:09:20Z Conference Object Orca IEEE Publications 2015 IEEE East-West Design & Test Symposium (EWDTS) 1 4
institution Open Polar
collection IEEE Publications
op_collection_id crieeecr
language unknown
format Conference Object
author Melikyan, Vazgen
Babayan, Eduard
Melikyan, Anush
Babayan, Davit
Petrosyan, Poghos
Mkrtchyan, Edvard
spellingShingle Melikyan, Vazgen
Babayan, Eduard
Melikyan, Anush
Babayan, Davit
Petrosyan, Poghos
Mkrtchyan, Edvard
Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
author_facet Melikyan, Vazgen
Babayan, Eduard
Melikyan, Anush
Babayan, Davit
Petrosyan, Poghos
Mkrtchyan, Edvard
author_sort Melikyan, Vazgen
title Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
title_short Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
title_full Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
title_fullStr Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
title_full_unstemmed Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
title_sort clock gating and multi-vth low power design methods based on 32/28 nm orca processor
publisher IEEE
publishDate 2015
url http://dx.doi.org/10.1109/ewdts.2015.7493159
http://xplorestaging.ieee.org/ielx7/7488713/7493093/07493159.pdf?arnumber=7493159
genre Orca
genre_facet Orca
op_source 2015 IEEE East-West Design & Test Symposium (EWDTS)
op_doi https://doi.org/10.1109/ewdts.2015.7493159
container_title 2015 IEEE East-West Design & Test Symposium (EWDTS)
container_start_page 1
op_container_end_page 4
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