Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor
Published in: | 2015 IEEE East-West Design & Test Symposium (EWDTS) |
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Main Authors: | , , , , , |
Format: | Conference Object |
Language: | unknown |
Published: |
IEEE
2015
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Subjects: | |
Online Access: | http://dx.doi.org/10.1109/ewdts.2015.7493159 http://xplorestaging.ieee.org/ielx7/7488713/7493093/07493159.pdf?arnumber=7493159 |
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